IP PORTFOLIO
Click on the Product line for a PDF product-brief. For full datasheet, please contact us
Product | Description | Standards and Features | Rating | Availability |
---|---|---|---|---|
MIPITMSVRPlus-8L-F | 8 lane 2nd Generation Serial Video Receiver for FPGA | CSI2 rev 2.0 DPHY rev 1.2 16 virtual channels 4 pixel output per clock calibration support Communication error statistics | 12Gbps | NOW |
MIPITM SVTPlus-8L-F | 8 lane 2nd Generation Serial Video Transmitter for FPGA | CSI2 rev 2.0 DPHY rev 1.2 | 12Gbps | NOW |
MIPITM SVRPlus2500 | 4-lane video receiver | CSI2 rev 2.0, DPHY rev 1.2 Low clock rating for easy timing closure PRBS support 4/8/16 output pixels per clock calibration support 1:16 input deserializers per lane 16 virtual channels | 4 x 2.5Gbps | NOW |
MIPITM SVTPlus2500 | 4-lane video transmitter | CSI2 rev 2.0 DPHY rev 1.2 Low clock rating for easy timing closure PRBS support 8/16 – pixel input per clock calibration support Programmable timing parameters 16 virtual channels | 4 x 2.5Gbps | NOW |
MIPITM CSI2MUX-A1F | CSI2 Video Multiplexor | CSI2 rev 1.3 DPHY rev 1.2 Receives inputs from up to four CSI2 cameras Outputs a single aggregated CSI2 video stream | 4 x 1.5Gbps | NOW |
MIPITM V-NLM-01 | Non Local Mean (NLM) image noise reduction hard core | Parameterized search-window size Parameterized number of bits per pixel Efficient implementation | HDMI (2048×1080) at 30 to 60 fps | NOW |
For ASIC versions of the IP cores, please contact us at ip_products@vlsiplus.com